1. Field of the Invention
The present invention relates generally to switch-capacitor (S-C) circuits, such as capacitors having unified architecture. More particularly, the invention is an improved switch (for a capacitor having unified architecture or another S-C circuit) which prevents capacitor charge loss which would otherwise result from overdriving the S-C circuit (e.g., during comparison of a reference potential with a previously sampled input potential). Overdriving of an S-C circuit results from applying a reference voltage that is significantly larger or smaller than an input potential previously sampled onto the input capacitor.
2. Description of the Related Art
FIG. 1 is a simplified block diagram of a conventional switch-capacitor (S-C) circuit having so-called "unified architecture." The expression "unified architecture" denotes that the circuit is used to compare the input potential V.sub.IN with at least two different reference potentials, i.e., the reference potentials denoted as V.sub.MAJ and V.sub.MIN in FIG. 1. The S-C circuit of FIG. 1 is used to sample V.sub.IN onto capacitor C, and also to provide voltage gain. Conventionally, switching circuitry S1 of FIG. 1 is implemented as three transmission gates S1A, S1B, and S1C connected in parallel (with each transmission gate including a PMOS transistor and a NMOS transistor connected in parallel, and being controlled by a complementary pair of the control signals "CONTROL"). Circuitry S1 can selectively couple to Node B any one of multiple input nodes (i.e., the input nodes at which potentials V.sub.IN, V.sub.MAJ and V.sub.MIN are asserted). The present invention pertains to an improvement over conventional implementations of switching circuitry S1, and to improved S-C circuits which include such improved switching circuitry.
Due to the conventional design of each of transmission gates S1A, S1B, and S1C, with the PMOS transistor of each transmission gate controlled by one of control signals "CONTROL" and the NMOS transistor thereof controlled by the complement of such control signal (the complement asserted to the gate of the NMOS transistor has opposite polarity to the control signal asserted to the gate of the PMOS transistor), any signal level of a selected one of the inputs can be transmitted when the transmission gate for such input is on, and any signal level of each non-selected one of the inputs can be blocked when both the NMOS and PMOS devices of the transmission gate for such input have been turned off. Usually the control signals for transmission gates S1A, S1B, and S1C will be non-overlapping, so that after sampling V.sub.IN (passing V.sub.IN through to Node B), switch S1A will be turned off before either S1B or S1C is turned on. The present invention pertains to an improvement over the conventional transmission gate implementation of switches S1A, S1B, and S1C, resulting in a substantial performance improvement of the S-C circuit in cases where the S-C circuit would otherwise experience overdrive. The term "overdrive" is used herein to denote the application of a reference voltage substantially different than the input voltage Vin.
The expression "switch-capacitor circuit" (abbreviated as "S-C circuit") is used herein to denote a circuit coupled to receive multiple input signals (each having a potential), and which includes a capacitor, a set of input switches controllable to assert a selected sequence of the input signals to one side of the capacitor, and circuitry (including at least one transistor, and typically including an amplifier) coupled to the other side of the capacitor. For example, an S-C circuit can be a capacitor having unified architecture if the circuitry coupled to the other side of the capacitor is appropriately designed to cause the S-C circuit to implement the function of a capacitor.
The design of the FIG. 1 circuit makes it useful in an analog-to-digital (A-to-D) converter. It is known to implement an A-to-D converter in which each of several circuits (each including an S-C circuit of the FIG. 1 type) compares an analog input voltage (V.sub.IN) to each of a number of reference voltages (e.g., to a "coarse comparison" reference potential V.sub.MAJ and a "fine comparison" reference potential V.sub.MIN). In such an A-to-D converter, the output (V.sub.OUT) of each implementation of the S-C circuit of FIG. 1 is an amplified version of the difference between V.sub.IN and V.sub.MAJ followed by the difference between V.sub.IN and V.sub.MIN, and is either amplified further by another S-C circuit or applied directly to a capacitor. Several channels, each consisting of an S-C circuit of the FIG. 1 type followed by further S-C circuits leading to a capacitor (or directly followed by a capacitor), can be implemented in parallel to implement a high-speed A-to-D converter. An A-to-D converter having such parallel configuration is typically referred to as a "flash" A-to-D converter. More specifically, since the circuit of FIG. 1 is designed for performing two comparisons, a coarse comparison between Vin and Vmaj followed by a fine comparison between Vin and Vmin, this configuration is known as a two-step flash architecture.
Typically, each control signal of the control signal set CONTROL of FIG. 1 is indicative of a binary bit, and a flash A-to-D converter would typically include several S-C circuits of the type shown in FIG. 1, each for comparing the input voltage V.sub.in (sequentially) with a different pair of coarse and fine reference voltages.
With reference to FIG. 1, analog input voltage V.sub.IN and reference voltages V.sub.MAJ and V.sub.MIN are supplied to different inputs of switching circuitry S1, one to each of transmission gates S1A, S1B, and S1C. Switching circuitry S selects any one of voltages V.sub.IN, V.sub.MAJ, and V.sub.MIN in response to the control signals identified as "CONTROL" in FIG. 1. The voltage signal selected by circuitry S1 (identified as "V.sub.INT ") is asserted to Node B. Capacitor C is connected between Node B and the input (Node A) of amplifier "Amp." The amplifier (Amp) needs to be an inverting amplifier, and can be as simple as an NMOS common source amplifier with a PMOS current load, whose voltage gain is set by the addition of a second capacitor between the amplifier's input and output.
Switch S2 (shown implemented as an NMOS transistor whose gate is coupled to receive control signal CONTROL2), connected between the input and output of amplifier Amp, is in either an open or closed configuration depending on the value of control signal CONTROL2. Switch S2 could alternatively consist of a transmission gate which is a parallel combination of an NMOS and PMOS device. However, typically switch S2 is a single NMOS device as shown, especially in implementations in which the virtual ground potential (Vb) established at the amplifier's input and output when S2 is closed is low (e.g., when Vb is 0.8 volt above ground, where ground is defined for purposes of this discussion as 0 volts). With switch S2 implemented as a single NMOS device, only large negative values of node A will result in charge loss from the plate of capacitor C that is coupled to Node A (by the NMOS source diffusions of switch S2 injecting charge into the substrate). Since all input voltages and supplies are typically above ground for single supply operation, we next explain how node A can be forced to a large negative potential during operation of a two-step flash A-to-D converter including the FIG. 1 circuit. During typical operation of such an A-to-D converter, control signals are asserted to switches S1A, S1B, S1C, and S2 to cause the FIG. 1 circuit to perform the following steps:
transmission gate switch S1A is closed to assert input potential V.sub.IN to Node B while switch S2 is closed so there is a virtual ground at Node A. Thus, Node A settles to a "virtual ground" potential Vb, and a charge Q=C(Vb-V.sub.IN)+C.sub.S Vb builds up on one plate of capacitor C, where C.sub.S is the stray capacitance at Node A. Virtual ground potential Vb is set by the characteristics of amplifier Amp. Sampling of V.sub.IN is accomplished by opening switch S2, after which charge Q represents a memory of the voltage V.sub.IN ; PA1 then, potential V.sub.MAJ is asserted to Node B to implement the "coarse comparison" (by opening transmission gate S1A and closing transmission gate S1B) while switch S2 is open. Ideally, there is no charge loss from capacitor C, Node A settles at a potential V', and the charge on the same plate of capacitor C is Q'=C(V'-V.sub.MAJ)+C.sub.S V'=Q. Thus, V'-Vb=C(V.sub.MAJ -V.sub.IN)/(C+C.sub.S). If V.sub.MAJ is equal to the previously sampled voltage V.sub.IN, then node A will be at Vb, and so will the output V.sub.OUT. This ignores nonideal effects such as the charge injected by switch S2 as it opens. The circuitry connected to the output of amplifier Amp will know that reference potential V.sub.MAJ is above the sampled input potential V.sub.IN if V.sub.OUT is below Vb, and that reference potential V.sub.MAJ is below the sampled input potential V.sub.IN if V.sub.OUT is above Vb; PA1 then, potential V.sub.MIN is asserted to Node B to implement the "fine comparison" (by opening transmission gate switches S1A and S1B and closing transmission gate switch S1C) while switch S2 is open. Ideally, there is no charge loss from capacitor C, Node A settles at a potential V", and the charge on capacitor C is Q"=C(V"-V.sub.MIN)+C.sub.S V"=Q. Accordingly (assuming no charge loss from capacitor C), V"-Vb=C (V.sub.MIN -V.sub.IN)/(C+C.sub.S). As before, the circuitry connected to the output of amplifier Amp will know that reference potential V.sub.MIN is above the sampled V.sub.IN if V.sub.OUT is below Vb, and that reference potential V.sub.MIN is below the sampled V.sub.IN if V.sub.OUT is above Vb. However, this is only true if the charge on the sampling capacitor C was not significantly disturbed during the coarse (previous) comparison.
In variations on the FIG. 1 circuit, more than two reference potentials are supplied as inputs to an implementation of switching circuit S1 that includes more than three transmission gates (and more than two comparisons are sequentially performed), or only a single reference potential (e.g., V.sub.MAJ) is supplied as an input to an implementation of switching circuit S1 that includes only two transmission gates and only a single comparison (of the reference potential with input potential V.sub.IN) is performed.
A problem with the conventional design of the S-C circuit of FIG. 1 (and variations thereon) is that if one of the reference potentials (e.g., V.sub.MAJ, which will be assumed to be the lower one of potentials V.sub.MAJ and V.sub.MIN in the following discussion) is much less than the sampled input potential V.sub.IN, the potential at Node A (potential V') plunges below ground potential (i.e., zero volts, in contrast with virtual ground potential Vb which is greater than zero volts) during the coarse comparison (the comparison of V.sub.MAJ and V.sub.IN). This can forward-bias the source diffusion of the NMOS device which implements switch S2, leading to charge loss from capacitor C. Overdrive of the S-C circuit during coarse comparison makes the subsequent fine comparison (of V.sub.MIN and V.sub.IN) inaccurate by virtue of errors introduced in the charge stored on capacitor C. Furthermore, this overdrive of the S-C circuit can be deleterious not just because of the charge loss on capacitor C, since the injected charge can undesirably be collected by adjacent circuitry. The collected charge can lead to errors on charge storage on other capacitors, can lead to noise in amplifiers, or even worse trigger latch-up (in which an unintended conduction path becomes active). For a specific difference V.sub.IN -V.sub.MAJ, the amount of charge injection or loss at node A depends on many parameters including the virtual ground potential and the relative magnitude of the capacitor C compared to the capacitance at the amplifier input and stray capacitance.
For example, if V.sub.IN =2.6 Volts; V.sub.MAJ =0.6 Volt; V.sub.MIN =2.48 Volts; and the virtual ground potential at Node A (when switch S2 is closed) is Vb=0.8 Volt, it is possible that there may be charge loss from capacitor C during comparison of V.sub.MAJ and V.sub.IN by the conventional S-C circuit of FIG. 1.
Until the present invention, it had not been known how to overcome the noted problem with conventional S-C circuits having unified architecture in a power efficient manner.